A logic analyzer is an electronic instrument used to analyze signals from a digital system or circuit. Such analysis may comprise, for instance, evaluation of timing, logic, or protocol adherence, among other things.
During typical operation, a logic analyzer is physically connected to a digital system or circuit to be analyzed (hereafter, the “target system”). This connection generally comprises mating between one or more pod connectors associated with the logic analyzer, and one or more footprints associated with the target system.
As used herein, the term “pod connector” denotes a physical grouping of connection interfaces (e.g., pins, pin receptacles, signal pads, etc.) associated with a logic analyzer, and the term “footprint” denotes a physical grouping of connection interfaces associated with a target system. The physical grouping of connection interfaces may include, for example, embedding them in a pluggable unit, such as a multi-pin connector head, or organizing a set of signal pads on a target board. A pod connector is typically mounted on one end of a logic analyzer cable, and a footprint is typically mounted on a board associated with the target system.
To properly analyze the signals from the target system, the logic analyzer must recognize correspondences between the connection interfaces of each pod connector and the signals provided through the corresponding footprint. In other words, it must recognize which signal of the target system is to be received through each connection interface of each pod connector.
In some scenarios, the logic analyzer can identify these correspondences through an automated or semi-automated setup process. For example, before analyzing signals on a double data rate (DDR) or low power DDR (LPDDR) memory bus, a logic analyzer may run a wizard-type setup program to guide a user in selecting an appropriate setup file for the memory bus. The setup file may define many (sometimes well over a hundred) signals on the DDR or LPDDR memory bus and map them to corresponding connection interfaces of a pod connector, which in turn correspond to logic analyzer channels. It may also conform to naming conventions that enable a signal decoder and compliance tools to work correctly, set up data viewers for ease of use, and initialize many other aspects of a logic analyzer graphical user interface (GUI) so that the user does not need to manage these setup details.
A typical logic analyzer provides setup files only for standard probing solutions. Accordingly, if a user has defined a non-standard set of pinouts to a logic analyzer, then no existing setup file will work without modifications. Making these modifications, however, can be cumbersome and error-prone, requiring the user to either go through hundreds of steps in a logic analyzer GUI or to modify a fairly cryptic XML file describing logic analyzer setup.
In view of these and other shortcomings of conventional approaches to logic analyzer configuration, there is a general need for improved approaches that can be used with target systems having non-standard connection interfaces.